The present invention relaters generally to a hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system comprises a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.
The advent of deep sub-micron technology has brought noise and signal integrity issues into the spotlight. The noise immunity issue is arguably more important than other design metrics such as area, timing and power, because if a circuit fails, it does not matter how small the circuit is, how fast it runs, or how little power it consumes. Therefore, to preserve signal integrity, every circuit must have a built-in noise margin to allow for possible signal degradation.
The noise problems for VLSI systems include leakage noise, charge-sharing noise, cross-talk noise, reflection noise and power supply noise. Leakage noise is due to the sub-threshold current of transistors. Charge-sharing noise is produced by the charge redistribution between the internal nodes and external nodes of a circuit. Cross-talk noise is the coupling noise between adjacent wires. Reflection noise occurs at each impedance discontinuity on a transmission line. Finally, power supply noise is the switching noise on the power supply lines, which is subsequently coupled onto the evaluation nodes of a circuit. For an under-damped low-loss network, the power supply noise problem can manifest itself in the form of a slowly decaying transient noise, or a potentially more dangerous resonance noise. As the power supply voltage and threshold voltage continue to scale down in deep sub-micron design, the noise margin will become very small, and control of power supply noise will be critical to determine the performance and reliability of very large scale integrated (VLSI) circuits.
Power supply noise can be simulated by modeling the inductance, resistance and capacitance of the power distribution network [H. Chen and D. Ling, xe2x80x9cPower supply noise analysis methodology for deep-submicron VLSI chip design,xe2x80x9d Design Automation Conference, June 1997, pp. 638-643]. However, it is difficult to verify the accuracy of simulation results without the actual hardware measurement data. Furthermore, for system-on-chip design, analog circuits, which are more susceptible to noise, may have multiple supply voltages that must be isolated from the digital circuits and analyzed separately [Y. Kashima et al., xe2x80x9cAn evaluation method for substrate noise in AD mixed-signal LSIsxe2x80x9d, Technical report of IEICE, IDC97-110, August 1997].
To calibrate the simulation model and provide a better estimate of the power supply noise, hardware measurement can be performed by using an amplification circuit to send the analog noise waveform off chip to an external tester [Hamid Partovi and Andrew J. Barber, xe2x80x9cNoise-free analog islands in digital integrated circuitsxe2x80x9d, U.S. Pat. No. 5,453,713]. This method is difficult to implement, however, due to the resolution required to measure high-frequency noise, and the large number of noise sources that need to be monitored. To minimize the possible noise interference in an analog circuit, a sampling method and multiple voltage comparators can be used to send the output to a digital tester [H. Aoki, M. Ikeda, and K. Asada, xe2x80x9cOn-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital testerxe2x80x9d, International Conference on Microelectronic Test Structures, March 2000, pp. 112-117].
Unfortunately, the use of clocks in the sampling circuit will limit the time resolution of noise measurement. The use of voltage comparators may also introduce uncertainty on the reference voltage due to the additional voltage drops.
Accordingly, it is a primary object of the present invention to provide a hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system comprises a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.